Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a power overlay (POL) packaging structure that incorporates a leadframe connection therein.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the device and protect the device from the external environment.
A standard POL package manufacturing process typically begins with placement of one or more power semiconductor devices onto a dielectric layer by way of an adhesive. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer to form a direct metallic connection to the power semiconductor device(s). The metal interconnects may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system to and from the power semiconductor device(s).
For connecting to an external circuit, such as by making a second level interconnection to a printed circuit board for example, current POL packages use solder ball grid arrays (BGAs) or land grid arrays (LGAs). While the short stand-off height (˜5 to 20 mils) of these types of interconnections provides a low profile, such connections are susceptible to early failure in high stress conditions. That is, very large temperature cycling ranges, shock, and vibration can induce failures in these solder joints.
Therefore, it would be desirable to provide a POL package having interconnections that are resistive to failure in high stress conditions, so as to enhance interconnection reliability. It would further be desirable for such a POL package to provide such reliability while minimizing cost of the POL package.